Open StudentHub

Studio Portfolio & Open Source

Shipped products, AI workflows & hardware tools.

Browse our live browser platforms, open-source automation repositories, Model Context Protocol (MCP) integrations, and digital logic design tools.

Launch StudentHub Request a Custom Build GitHub Repositories

Next.jsReactPythonC / C++JavaVerilogPDF Engine

Flagship Platforms

Live browser workspaces

Production applications running directly in the browser with zero local setup.

live

StudentHub

Four everyday student tools in one clean browser workspace.

Web IDECompilersPDF

live

Verilog Lab

Design circuits, run testbenches, and inspect live waveforms.

VerilogWaveformsSynthesis

Open-Source & Studio Builds

All shipped repositories & workflows

Filter by AI & Automation or Circuits & Verilog to inspect individual tools and source code.

Jules MCP Server

Python server connecting AI coding agents to Git workflows and pull requests.

PythonMCPAutomation

AI Circuit Generator

Turns plain-English prompts into tested Verilog circuits and waveforms.

AIVerilogSimulation

Auto Scheduler

Desktop workflow tool that runs scheduled tasks and visual click actions.

AI Discord Assistant

Smart community bot for automated replies, moderation, and server utilities.

Live Market Streamer

Real-time WebSocket client streaming live market data into clean dashboards.

PythonWebSockets

Natural Language to RTL

Describe a circuit in plain words to generate, test, and synthesise it.

VerilogAISynthesis

Browser Circuit Simulator

Write Verilog, run simulations, and inspect signal waveforms online.

VerilogWaveforms

Engineering Architecture

Built for reliability, speed, and clean handover

Every project we ship—whether an open-source student utility or a custom client system—follows strict engineering standards.

Model Context Protocol (MCP) & AI Agents

Production Python and TypeScript servers that connect LLM coding agents directly to Git repositories, issue trackers, and automated pull-request pipelines.

Browser-Native EDA & Hardware Verification

Zero-install IEEE 1364 / 1800-2012 Verilog simulation, VCD waveform inspection, and Yosys gate-level netlist synthesis running in isolated sandboxes.

Full-Stack Web & Realtime Systems

High-throughput WebSocket market streamers, desktop task schedulers, and multi-language code execution engines built for speed and reliability.