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Nemofy · Hardware

Verilog hardware blueprints

Real RTL flows: natural-language → RTL → testbench → simulate → synthesize. No fabricated results — what runs is what's shown.

AI VerilogLab (NL → RTL → synth)

Planner → generator (self-checking testbenches) → simulator (Icarus 12, ≤3 fix retries) → synthesizer (Yosys synth + stat JSON) → waveform PNG/SVG. Mock mode works fully offline.

VerilogIcarus 12Yosys 0.52Python

Runs live inside Student Hub → AI VerilogLab, backed by /api/ai-verilog/*

Verilog Lab (simulate in browser)

In-browser Verilog editor with sandboxed simulation (unshare -rn, no network for user code), VCD waveform viewing. Backed by /api/verilog/simulate.

VerilogIcarus 12VCD

The AI VerilogLab flow

  1. 1Plan. Strict 5-phase JSON: rtl → testbench → simulate → synthesis → report.
  2. 2Generate. RTL plus self-checking testbench ($dumpfile/$dumpvars, PASS/FAIL, $finish).
  3. 3Simulate. iverilog -g2012 + vvp with timeouts; error classification; ≤3 fix retries.
  4. 4Synthesize. Yosys synth with JSON stats and text reports.
  5. 5Waveform. VCD parsed to PNG/SVG; open dump.vcd in GTKWave for full view.

Try it live: AI VerilogLab · Verilog Lab simulator. Toolchain: Icarus Verilog 12, Yosys 0.52, sandboxed execution with no network for user code.